
`include "defines.v"

module mux_alu_ib (
    input  wire              rst,
    
    input  wire [`BUS_WIDTH] r_data2,
    input  wire [`BUS_WIDTH] imm,
    input  wire [1 :      0] alu_bsrc,

    output reg  [`BUS_WIDTH] alu_ib
);


    always @(*) begin
        if (rst) begin
            alu_ib = `ZERO_WORD;
        end
        else begin
            case (alu_bsrc)
                2'b00: begin
                    alu_ib = r_data2;
                end
                2'b01: begin
                    alu_ib = 64'b100;
                end
                2'b10: begin
                    alu_ib = imm;
                end
                default: begin
                    alu_ib = `ZERO_WORD;
                end
            endcase
        end
    end

    
endmodule
